VLSI System Design Laboratory Technical Report:TR-VSD-803.1 Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
نویسندگان
چکیده
System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.
منابع مشابه
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip
System level design always has a disadvantage of not possessing detailed knowledge of the communication sub-system. This is a crucial issue for System-on-Chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The algorithm is part of ...
متن کاملSignal Encoding Schemes for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. We obtain the lower and upper bounds on coupling effects for randomly distributed, independent data streams based on the information theory. Novel low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the on-chip bus power consumptio...
متن کاملCapacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Capacitor-couple technique used to lower snapbacktrigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-coup...
متن کاملExploiting intellectual properties with imprecise design costs for system-on-chip synthesis
This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is conv...
متن کاملModeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design
This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...
متن کامل